Plasma Technology for Advanced Devices
Preview of the 2004 VLSI Technology Symposium
Several companies will report on using high k dielectrics in combination with metal gates or silicon gates for low power applications. SAMSUNG submitted a paper on embedded SRAM technology with HfO2-Al2O3. NEC will present on a 65nm-node Poly-Si/a-Si/HfSiON transistor with a thin amorphous-Si layer between the HfSiON and the phosphorous-doped poly-Si gate-electrode for improved reliability. STM will unveil 55 nm pMOSFET transistors with compressively strained SiGe(:C) channels, TiN metal on HfO2 gates as well as sub-100nm TaSiN metal gate fully-depleted SOI devices with HfO2 gate dielectrics. IBM will report on fully silicided (FUSI), dual work function, Ni monosilicide metal gates using Sb pre-doped poly-Si for setting the nFET workfunction and a combination of Al predoped poly-Si and a Ni(Pt) alloy silicide for the pFET workfunction. In two other papers, IBM will show dual work function metal gates with poly-Si/metal nitrides on SiON or high-k stacks with atomic layer deposition TaNx for the NFET and ALD-WNx for the PFET as well as dual workfunction metal gated MOSFETs with CVD TaSiN, W and Re on HfO2. IMEC will demonstrate fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics. It will be shown that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs.
Drive current improvements by silicon strain engineering will be another focus of attention. A joint paper by Texas Instruments, UT Dallas and Applied Materials will report on 35% drive current improvements from recessed-SiGe drain extensions in 37 nm gate length PMOS devices. IBM will discuss a novel process flow which creates circuits with independently oriented surface channels for pMOS and nMOS devices by integrating FinFETs with planar ultra-thin SOI (UTSOI) MOSFET’s. This concept is called Simplified Hybrid Orientation Technology (SHOT).
Among the less traditional processes, plasma doping and laser annealing for the formation of shallow and abrupt junctions seem to occupy a prominent place. A joint team by STM, Motorola and Varian will present a high performance 65nm CMOS device fabricated with plasma doping and standard spike annealing activation. A paper by the Tokyo Institute of Technology and Ultimate Junction Technology will cover B2H6 Plasma Doping with "In-situ He pre-amorphization". Ultra-shallow p+/n junctions were verified by flash lamp annealing and laser annealing. Hitachi and Ultratech will report on ultra-shallow junction formation by non-melt laser spike annealing (LSA) for 50-nm gates. It was found that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.
Among the alternative devices which will be presented in Hololulu are 5nm-gate nanowire FinFETs by TSMC, sub-50 nm Multi-Bridge-Channel MOSFET (MBCFET) by SAMSUNG and CPU’s on a plastic film substrate by Semiconductor Energy Laboratory Corporation.
Interestingly, FeRAM papers will outnumber MRAM and PRAM papers (3, 2, and 2 submissions, respectively).