Reference

Device / Process Details

L gate

Vdd

EOT

NMOS Idsat

PMOS Idsat

NMOS Ioff

PMOS Ioff

NMOS Swing

PMOS Swing

NMOS CV/I

PMOS CV/I

NMOS Cgd

PMOS Cgd

NMOS DIBL

PMOS DIBL

nm

V

A

μA/μm

μA/μm

nA/μm

nA/μm

mV/dec

mV/dec

ps

ps

fF/μm

fF/μm

mV/V

mV/V

F.-L. Yang et al. / TSMC / VLSI 2002, p. 104

FinFET, in-situ N+, Co salicide

35

1.0

24

1240

500

200

200

78

96

0.65

1.70

M. Mehrotra et al. / TI / VLSI 2002, p. 124

193nm litho, dual spacers, Co salicide

60

1.3

17.5

1160

550

100

100

0.29

0.29

R. Tsuchiya et al. / Hitachi / VLSI 2002, p. 150

high-k offset spacers, Co salicide

40

1.0

14

680

300

10

10

0.80

1.68

C.C. Wu et al. / TSMC / IEDM 2002

90 nm node High Soeed, SSR In/As channels, nitrided Gox, CoSix

45/50

1.0

< 14

830

380

75

75

N. Yanagiya et al. / Toshiba/Sony / IEDM 2002

65 nm node (HP) Si/Ge gate, NiSix, offset spacer, nitrided Gox

30

0.85

10

700

300

100

100

0.28

0.28

Y.W. Kim et al. / SAMSUNG / IEDM 2002

90 nm node, notche gate, SSR In/As channels, CoSi2, high speed MPU

50

1.0

13

850

360

90

90

Y. Momiyama et al. / Fujitsu / IEDM 2002

NO nitrided Gox, N-tub extension, p-MOSFET

40

1.0

22

382

100

120

1.65

F.L. Yang et al. / TSMC / IEDM 2002

25 nm Omega FET

25

0.7

17 - 19

1300

550

1000

1000

0.39

0.88

B. Yu et al. / AMD / IEDM 2002

10 nm double gate FinFET

10 per gate

1.2

17

446

365

125

101

0.34

0.43

71

120

J. Kedzierski et al. / IBM / IEDM 2002

Metal-gate FinFET, undoped body, RSD, CoSi2 S/D, NiSi gate

100

1.25

16

970

600

120

20

70

70

25

25

B. Doris et al. / IBM / IEDM 2002

FD-SOI p-FET, 4.6 nm channel, undoped channel, RSD, CoSi2

14

1.2

12

328

186

71

24

S. Monfray et al. / STM / IEDM 2002

Co silicided P-MOSFET, SON w. 5 nm thick channel

55

1.4

20

350

0.1

73

60

K. Matsuo et al. / Toshiba / IEDM 2002

Damascene gate with recessed channel, CoSi2

35 / 55 n / p

1.0

15

963

327

79

85

84

109

67

148

A. Hokazono et al. / Toshiba / IEDM 2002

SiGe gate, NiSi, offset spacers, plasma nitrided Gox

14

0.75

10

564

251

251

185

0.35

0.82

B.S. Doyle et al. / Intel / IEEE Electron Device Letters; 24 (2003) 263

Tri-gate, TSi=36 nm, WSi=55nm, no halo implants, raised source drain

60

1.3

15

521

660

70

24

68

69.5

41

48

V. Chan et al. / IBM / IEDM 2003

bulk transistor, 90 nm node, strain from STI and nitride

45

1.0

12

1010

400

100

100

85

85

100

100

B. Doris et al. / IBM / IEDM 2003

ultra thin SOI, raised extentions, poly-Si on SiON (W on HfO2 also reported)

8

1.5

9

340

320

90

80

0.62

0.61

T. Ghani et al. / Intel / IEDM 2003

90 nm node. epitaxially grown strained SiGe film embedded in the source drain regions

45 / 50 n / p

1.2

12 (phys.)

1260 - 1450

700 - 800

40 - 400

40 - 400

< 100

< 100

S. Datta / Intel / IEDM 2003

strained Si channel with HfO2 dielectric and TiN metal gate

80

10

930

0.001

72

49

S. G. Park / SAMSUNG / IEDM 2003

HfO2-Al2O3 laminate gate dielectric with CVD-TaN metal gate

110

1.5

4SiO2
35 HfAlO phys.

839

468

60

0.007

87

86

J. H. Yang / SAMSUNG / IEDM 2003

Triple gate, H bake for surface roughness control, SiON gate dielectric

45

0.85

13

254

276

18

136

80

88

S. Harrison / STM, LETI, Philips, L2MP / IEDM 2003

Double gate SON

70

1.2

20

1333 - 1954

1- 283

70 - 80

30 - 70

F. L. Yang / TSMC / IEDM 2003

SOI, slim spacer

40

1.0

12

1015

500

40

40

B. Doris / IBM / VLSI 2004

Simplified Hybrid Orientation Technology (SHOT), FinFET

50

1.2

14

715

810

26

1000

75

90

68

45

H. Wang / TSMC / IEDM 2004

Strained SiGe channel, HfSiON

80

1.2

15

420

197

0.025

0.01

80

90

80

130

K. Goto / Fujitsu / IEDM 2004

Laminated SiN capping layer, SiON gate dielectric

37

1.0

12

1120

100

96

0.61

T. Komoda / Toshiba, Sony / IEDM 2004

<100> oriented channel with high tensile stress SiN gate capping layer

35

1.0

13

865

415

100

100

S. Harrison / STM, Philips, LETI / IEDM 2004

Poly-gate replacement through contact hole, HfOx, TiN

90

1.2

18

1040

820

3.3

1.5

95

100

50

63

E.-J. Yoon / SAMSUNG / IEDM 2004

Multi Bridge Channel, silicon oxide gate dielectric / TiN gate

30

1.2

20

2310

75

36

K. Henson / IMEC / IEDM 2004

TaN on SiON gate dielectric, etched gate electrode

45

1.2

12

1150

10

W.-H. Lee / IBM, Toshiba, AMD / IEDM 2005

SOI, Dual Stress Liner, SiGe

> 30

1.0

10.5

1259

735

200

200

108

112

H. Wakabayashi / NEC / IEDM 2005

planar bulk CMOS, eSDE, Si-SEG

6

0.9

12

92.6

258

2330

38500

P. Ranade / Intel / IEDM 2005

NiSi Metal Gate (FUSI), Uniaxial Strained Silicon

35

1.2

12

1750

1060

100

100

C.-Y. Sung / IBM / IEDM 2005

Bulk CMOS, Direct Silicon Bond (DSB) Mixed Crystal Orientation Substrates

45

1.0

12

1000

440

40

1

H.Ohta / Fujitsu / IEDM 2005

Bulk CMOS with Sigma-shaped SiGe-SD

30

1.0

12

937

490

100

100

100

103

0.59

0.99

Z. Luo / IBM, Chartered / Infineon / Toshiba / IEDM 2005

eSiGe junctions, compressively stressed nitride liner (CSL)

43

1.0

11

640

50

S. D. Suk / SAMSUNG / IEDM 2005

Twin Silicon Nanowire MOSFET (TSNWFET), NMOS TiN

30

1.0

20

2640

1110

3.1

0.006

70

70

20

20

K. Okano / Toshiba / IEDM 2005

FinFET

30

1.0

800

800

80

80

T. Hirano / Sony / IEDM 2005

HfSix/HfO2 Metal Gate

66

1.3

16

1250

1

78.6