US Patent Number | Title | Assignee | Date of Patent |
6696333 | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes | Intel Corporation | 2/24/2004 |
6696334 | Method for formation of a differential offset spacer | Advanced Micro Devices, Inc. | 2/24/2004 |
6696345 | Metal-gate electrode for CMOS transistor applications | Intel Corporation | 2/24/2004 |
6699399 | Self-cleaning etch process | Applied Materials, Inc. | 3/2/2004 |
6699763 | Disposable spacer technology for reduced cost CMOS processing | Texas Instruments Incorporated | 3/2/2004 |
6699777 | Etch stop layer in poly-metal structures | Micron Technology, Inc. | 3/2/2004 |
6699779 | Method for making nanoscale wires and gaps for switches and transistors | Hewlett-Packard Development Company | 3/2/2004 |
6699795 | Gate etch process | Cypress Semiconductor Corp. | 3/2/2004 |
6701511 | Optical and etch proximity correction | LSI Logic Corporation | 3/2/2004 |
6703170 | Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process | DuPont Photomasks, Inc. | 3/9/2004 |
6703312 | Method of forming active devices of different gatelengths using lithographic printed gate images of same length | International Business Machines Corporation | 3/9/2004 |
6706138 | Adjustable dual frequency voltage dividing plasma reactor | Applied Materials Inc. | 3/16/2004 |
6706569 | SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same | Samsung Electronics Co. | 3/16/2004 |
6706605 | Transistor formed from stacked disposable sidewall spacer | Texas Instruments Incorporated | 3/16/2004 |
6706614 | Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation | Advanced Micro Devices, Inc. | 3/16/2004 |
6706623 | Method and system for avoiding plasma etch damage | Texas Instruments Incorporated | 3/16/2004 |
6707062 | Transistor in a semiconductor device with an elevated channel and a source drain | Hyundai Electronics Industries Co. | 3/16/2004 |
6707562 | Method of using scatterometry measurements to control photoresist etch process | Advanced Micro Devices, Inc. | 3/16/2004 |
6709547 | Moveable barrier for multiple etch processes | Lam Research Corporation | 3/23/2004 |
6709807 | Process for reducing edge roughness in patterned photoresist | Axcelis Technologies, Inc. | 3/23/2004 |
6709911 | Method for making a semiconductor device having a high-k gate dielectric | Intel Corporation | 3/23/2004 |
