6/16/2005
UMC announces at the 2005 VLSI symposium that it reduced the so-called Equivalent Oxide Thickness (EOT) of nitrogen doped silicon oxide (Oxy-nitride, SiON) gate dielectrics to approximately 1.0 nanometer using a nitrogen profile engineering technique. Source: EE Times 6/11/2003
United Microelectronics Corp. gave details of the use of 'strained silicon' for a 70-nm manufacturing process technology at the Symposium on VLSI Technology in Kyoto. The transistorwas made using wafers based on technology from Source: '
| 
