Plasma Technology for Advanced Devices

1/12/2006
IBM, Sony and Toshiba announce that they will extend their joint work on fundamental research related to new chips, including materials research. The three companies have been working together for several years on 45 nm technology and the new agreement will extend this collaboration to 32 nm. The development work under the new deal will take place at three locations in New York state: IBM's Thomas J. Watson Research Center in Yorktown Heights, the Center for Semiconductor Research at Albany Nanotech, and at IBM's chip factory in East Fishkill. In August 2005, IBM announced that it will extend the collaboration with AMD on 32- and 22-nm process and chip technologies through 2011. Source: Network World

8/25/2005
IBM, Toshiba and Sony release the detailed specifications of the cell processor. Source: www.ibm.com

6/16/2005
Toshiba and SONY announce at the 2005 VLSI Symposium that they used for the 45 nm CMOS6 embedded dRAM technology a bottle etching process combined with a structure named LOCOS collar, which allows forming the trench in a bottle like shape. In addition to the bottle-like shape for the trench, high-K node dielectric material (Al2O3) is used in place of conventional nitride-oxide insulation. Source: EE Times

2/7/2005
IBM, Toshiba, and Sony disclose in detail the breakthrough multi-core architectural design - featuring supercomputer-like floating point performance with observed clock speeds greater than 4 GHz - of their jointly developed microprocessor code-named Cell. Source: www.ibm.com

1/12/2004
Sony and Toshiba announce that they would collaborate in the development of highly advanced 45 nm process and design technologies for next-generation system LSI. Under the terms of an agreement, the two companies will take their successful development of 65nm process technologies to the next level, with positive results expected in 2005. Source: www.toshiba.co.jp

12/15/2003
Toshiba Corp. and Sony Corp. announced that they will begin offering by March engineering samples of a 65-nanometer embedded-DRAM technology. The design includes a 30 nm gate. Source: Silicon Strategies

12/7/2003
IBM, AMD, Toshiba, and Sony present at the IEDM conference a 90 nm device with partially depleted SOI with 40 nm gate length, raised source/drain, disposable spacer, final spacer for S/D doping and silicide proximity, and NiSi.

4/2/2002
IBM Corp., Toshiba Corp., and Sony Corp., announce plans to co-develop advanced process technologies on 300-mm wafer substrates. The R&D partnership is aimed at on 90-nm, 65-nm , and 45-nm technology nodes based on several advanced process technologies and materials, such as SOI wafers, copper-metal interconnects, and low-k dielectrics. In addition, IBM will transfer its SOI technology to Japan's Sony and Toshiba. A team of scientists and engineers from IBM, Sony, and Toshiba will co-develop SOI technologies and devices at IBM's Semiconductor Research and Development Center (SRDC), based in East Fishkill. Source: SBN

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