Clarycon News Archive: Texas Instruments 6/13/2007
Ti announces plans to integrate hafnium based high k materials in its high-performance chips at the 45-nm node. TI will use a chemical vapor deposition (CVD) process to deposit hafnium silicon oxide (HfSiO), followed by a reaction with a downstream nitrogen plasma process to form HfSiON or hafnium silicon oxynitride. 1/24/2007
TI announces that the company has decided to stop internal development at the 45-nanometer node and use foundry supplied processes at 32-nm, 22-nm and thereafter. 6/12/2006
TI announces that it will stop short of introducing a high-k dielectric at the 45nm node. TI will use a conventional gate stack of nitrided silicon dioxide and a polysilicon gate for both its low-standby-power process (for cell phones) and its high-performance process for (digital signal processors). For a 45-nm process developed to manufacture microprocessors for Sun Microsystems, TI plans to introduce a metal gate electrode to reduce the polysilicon depletion effect, which degrades the oxide's electrical performance. It has not yet been decided whether deposited metal gates will be used or whether the gate electrodes will be ormed using a fully silicided method. At the 32-nm node, TI plans to combine the metal gate with a high-k dielectric. Source: EE Times 10/13/2003
Texas Instruments Inc. announces that it 's 90 nm manufacturing process technology for its high-performance client Sun Microsystems Inc. includes 37 nm gate length, strained silicon to increase mobility, nickel-silicide interfacial gate layers to lower gate resistance and ultra-shallow source and drain diffusions. Source: Silicon Strategies
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