Plasma Technology for Advanced Devices

2/25/2008
Qimonda AG Technologies announces announced its technology roadmap down to the 30nm generation and featuring cell sizes of 4F. Qimonda is introducing this leading edge technology now in 65nm and plans to begin production of a 1 Gbit DDR2 in the second half of calendar 2008.

1/31/2006
Infineon Technologies announces that it has produced first sample chips in its advanced 65nm low-power and high-performance CMOS platform technology. Infineon leveraged the results of the industry leading 65nm/45nm alliance composed of IBM, Chartered, Infineon, and Samsung (ICIS). The wafer production was done in the frame of the manufacturing partnership with Chartered. Source: www.infineon.com

11/22/2004
Infineon reports that it has developed the worlds smallest carbon nanotube transistor. The nanotube transistor can deliver currents in excess of 15 A at a supply voltage of only 0.4 V (0.7 V is currently the norm). Source:
Infineon

9/21/2004
Axon Technologies Corp. announces that Infineon Technologies AG has licensed its next-generation, nonvolatile memory technology.

8/26/2003
Infineon Technologies announces that it shipped first samples of its 1-Gbit DDR SDRAM to some customers. The devices are fabricated using the company’s advanced 110nm CMOS process. At only 160mm˜ chip size they are the industry’s smallest 1-Gbit DDR SDRAMs to date. Source:
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8/13/2003
Infineon Technologies Infineon Technologies AG forms a $12 million joint venture with (UEC) of Taiwan, a maker of fiber optic components.

6/13/2003
Infineon Technologies presents at the VLSI Symposium in Kyoto on the following subjects:

Paper 13-1 - Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM
Infineon, Toshiba
This paper describes key circuit features for further optimization of the Chain FeRAM (Ferro-electric Random Access Memory) chip architecture. This architecture allows for high memory density on small chip area with ultra low stand-by power dissipation. The novel circuit features, which significantly increase the signal margin and product yield, as well as the product reliability include a three-level plate line drive scheme for reduction of the gate oxide stress and a capacitive balancing scheme for increased signal margin, are presented. The FeRAM circuit schemes are implemented on a 32Mb Chain FeRAM product chip, which is a joint development of Toshiba Corp., Japan, and Infineon Technologies.

Paper 2-4 – A 0.18 m Logic-based MRAM Technology for High Performance Nonvolatile Memory Application
Infineon, IBM
This paper discusses the fabrication of a 128Kb MRAM (Magnetoresistive Random Access Memory) using the world’s smallest MRAM cell size with only 1.4 square micron. The nonvolatile memory chip was fabricated on a standard 0.18 micron logic based process with three copper metallization layers and a 1T1MTJ (1 Transistor, 1 Magnetic-Tunnel-Junction) architecture. Repeated write cycles of the test array shows excellent endurance with no degradation through 630 million write cycles.

Paper 16-4 - A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications
Infineon, IBM
The paper describes a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations of measurements from the 128Kbit MRAM test chip described in the above abstract and circuit assessments predict a 5ns random array read access time and random write operations with less than 5ns write pulse width. These results highlight the high performance capabilities of the 1T1MTJ architecture of the MRAM technology.

Paper 12A-1 – Direct Measurement of the Inversion Charge in MOSFETs; Application to Mobility Extraction in Alternative Gate Dielectrics
Infineon, IBM, IMEC, KU Leuven, International Sematech, Institut fr Halbleitertechnik TU-Darmstadt
Scaled MOSFETs using alternative gate dielectrics show strongly reduced carrier mobility. Conventional measuring techniques to determine the carrier mobility and the possible causes for the reductions are not reliable for FETs (Field Effect Transistors) with alternative gate dielectrics, because of strong charge trapping during the measurements.

This paper introduces Inversion Charge Pumping (ICP) as a new alternative method to measure the “true” inversion charge in n-channel FETs. The method was used to extract the mobility in FETs with conventional and SiO2/HfO2 dual layer gate dielectrics. It was demonstrated that charge trapping and net-fixed charge in n-channel MOSFETs are not the primary cause for the strong mobility degradation. This new measurement method with the related results on carrier mobility and charge trapping is a mayor step in the integration of new alternative dielectric materials in future CMOS chip technologies.

Paper 12A-3 – Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the Interfacial Oxide
Infineon, IBM, IMEC, International Sematech, KU Leuven
To fulfil high performance requirements as the feature size of future chip generations shrinks, a lot of effort is concentrated on research and development of high isolation (high-k) alternative dielectrics to replace conventional silicon oxide. It has been shown that observed threshold voltage instability in SiO
2/HfO2 dual layer gate stacks can be explained by charging and discharging of pre-existing defects in the gate stack.

This paper demonstrates that the threshold voltage instability of the HfO2 (Hafnium oxide) gate dielectrics is controlled by the dynamics of the electron trapping and detrapping in the HfO2 bulk defects. Therefore the measured magnitude of the instability depends critically on the gate leakage, the electric field, the lattice temperature and the timing of the used measurement procedure. It is also shown that the interfacial oxide thickness influences the mechanism of charging and discharging of the HfO2 defects. When the thickness is reduced, trap filling by electron tunnelling appears to contribute to the instability effects. So the bulk trapping properties of the HfO2 layers have to be controlled - otherwise the threshold voltage instability threatens the high-k dielectric integration in future CMOS processes.

6/11/2003
Infineon Technologies and Clariant Corporation’s AZ Electronic Materials business sign an agreement to jointly develop photoresists for 157 nm exposure technology. The goal is to accelerate qualification of this technology for volume production. The photoresist materials to be developed in this project will specifically enable Infineon to qualify the 157 nm technology for producing 55 nm structures in DRAM (dynamic random access memory) semiconductor chip production. Source: '

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