Plasma Technology for Advanced Devices

OPEN HOUSE FOR SENIOR PROCESS ENGINEERS

Dallas Semiconductor/Maxim will conduct interviews on July 12th and 13th in the downtown San Francisco area. Location will be disclosed upon scheduling of interviews.

Please RSVP by forwarding your resume to: Recruiter@dalsemi.com reference Job # 1137 no later than Friday, July 8.

Positions available in Dallas, Texas.
www.maxim-ic.com

Open Positions:
Sr. Thin Films Process Engineer
Sr. Process Engineer Metal Etch
Sr. Process Engineer / Sr. MTS Gate Oxide Integrity

Sr. Thin Films Process Engineer

Education:
BS or higher in material science, physics, chemistry electrical, chemical, or mechanical engineering.

Knowledge:
Knowledge of common film properties and metrology techniques involved in Thin films ensuring process control such as thickness, stress, Refractive index, FTIR.

Understanding of reaction kinetics of dielectric film deposition in a PECVD reactor with specific knowledge of Novellus PECVD tools including precursors used and delivery systems associated with them.

Understading of SPC, Design of Experiments and Statistical Data Analysis techniques.

Experience:
5 years or more hands on experience inside wafer fab, 3 years or more of which in area of thin films

Personality:
Demanding, persistent, curious, and very detail oriented.

Description of duties:
1) Establish and maintain SPC and process control in the area of Thin Films
2) Recruit and train junior level engineers and technicians.
3) Identify current process monitor deficiency, propose new control techniques if adequate.
4) Manage and implement operating procedures for the thin film area in PECVD
5) Work closely with equipment engineers to maintain PECVD tool uptime and respond to excursions.
6) Develop process improvements and new process development according to the needs of changing technology.

Sr. Process Engineer Metal Etch

Education:
BS or higher in material science, physics, chemistry electrical, chemical, or mechanical engineering.

Knowledge:
Knowledge Metal etch process and equipment. Experience in troubleshooting coroison, residue, bridging for Al/Cu stack with TiN/TiW ARC and barrier films. Knowledge of post etch clean up including strip/passivation sequence and solvent clean up post metal etch for residue free process. Defect monitoring using inline SEM.

Understanding of reaction kinetics of Cl2 plasma as used in conductor etching for profile, CD control and microloading. Exposure to plasma diagnostics such as Optical emission spectroscopy based end point, insitu wafer temperature measurement, RF matching network.

Preferably experience in high density conductor etchers such as Lam 9600 or AMAT DPS.

Understading of SPC, Design of Experiments and Statistical Data Analysis techniques.

Experience:
5 years or more hands on experience inside wafer fab, 3 years or more of which in area of Plasma Etch

Personality:
Demanding, persistent, curious, and very detail oriented.

Description of duties:
1) Establish and maintain SPC and process control in the area of Metal etch
2) Recruit and train junior level engineers and technicians.
3) Identify current process monitor deficiency, propose new control techniques if adequate preferably using tools such as Lam station
4) Improve tool uptime by improved PM procedures and process optimization.
5) Manage and implement operating procedures for the Metal etch area in Plasma
6) Work closely with equipment engineers to maintain Metal etch tool uptime and respond to excursions.
7) Develop process improvements and new process development according to the needs of changing technology.

Sr. Process Engineer / Sr. MTS Gate Oxide Integrity

Education:
BS or higher in electrical, chemical, or mechanical engineering, material science, physics, or chemistry. BSEE/MSEE preferred.

Knowledge:
Thorough knowledge of:
- gate oxide integrity
- factors that affect GOI
- diffusion processes
- oxidation processes
- failure analysis techniques for gate oxide failures
- front-end process integration and its effects on GOI

Experience:
5 years or more in process engineering or yield enhancement

Personality:
Energetic, aggressive, detail-oriented, problem-solving.

Description of duties:
1) Monitor GOI for 6” and 8” production fabs.
2) Maintain a trend chart of gate oxide defect density across all technologies and processes.
3) Setup and maintain an inline GOI measurement tool.
4) React to excursions and determine root cause.
5) Correlate gate oxide defect density to yield and infant mortality failure rate
6) Drive continuous improvement in device reliability
7) Evaluate and implement improved Si substrates
8) Eliminate burn-in

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