Plasma Technology for Advanced Devices


Volume 20: December 2004
IEDM 2004

Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-k Dielectrics: Enhanced Performance at Reduced Gate Leakage
E.P. Gusev, C. Cabral, B.P. Linder, Y.H. Kim, K. Maitra, E. Cartier, H. Nayfeh, R. Amos, G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S.A. Cohen, M. Copel, S. Fang, M.Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. Ieong, J. Kedzierski, P. Kozlowski, V. Ku, D. Lacey, D. LaTulipe, V. Narayanan, H. Ng, P. Nguyen, J. Newbury, V. Paruchuri, R. Rengarajan, G. Shahidi, A. Steegen, M. Steen, S. Zafar, and Y. Zhang

This paper demonstrates a significant gate leakage reduction and drive current improvements for FUSI/HfSixOy gate stacks. The use of HfSixOy is reported to be essential to achieve good mobility. The threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt (PFET) about -0.4 V and Vt (NFET) of about + 0.3 V by poly-Si pre-doping by implantation of Al or As.

 

Selectively Formed High Mobility Strained Ge PMOSFETs for High Performance CMOS
Huiling Shang, Jack O. Chu, Stephen Bedell, Evgeni P. Gusev, Paul Jamison, Ying Zhang, John A. Ott, Matthew Copel, Devendra Sadana, Kathryn W. Guarini, Meikei Ieong

The selectively formed compressively stressed Ge channels are realized on pre-patterned SGOI regions by local thermal mixing (TM) or UHVCVD processing. The thinnest ever SiO2 (2.5nm) on s- Ge channel MOSFETs is demonstrated by low temperature remote plasma oxidation of a thin Si cap while maintaining the strain in the Ge layer. A three times PMOSFET drive current enhancement is reported.

 

Technology Booster using Strain-Enhancing Laminated SiN (SELS) for 65nm Node HP MPUs
K.Goto, S.Satoh, H.Ohta, S.Fukuta, T.Yamamoto, T.Mori, Y.Tagawa, T.Sakuma, T.Saiki, Y.Shimamune, A.Katakami, A.Hatada, H.Morioka, Y.Hayami, S.Inagaki, K.Kawamura, Y.Kim, H.Kokura, N.Tamura, N.Horiguchi, M.Kojima, T.Sugii, and K.Hashimoto

Compared ti a SiN layer with the same thickness and stress, multi layer deposition is found to enhance the channel strain. High performance 37nm gate nMOSFETs and 45nm gate pMOSFETs were demonstrated with a drive currents of 1120 microamps/micrometer and 690 microamps/micrometer at Vdd=1V / Ioff=100 nA/micrometer, respectively.

For transistor performance comparison, follow this link.

 

Mobility Improvement for 45nm Node by Combination of Optimized Stress Control and Channel Orientation Design
T. Komoda, A. Oishi, T. Sanuki, K. Kasai, H. Yoshimura, K. Ohno, M. Iwai, M. Saito, F. Matsuoka, N. Nagashima and T. Noguchi

By using <100>-channel, a higher drive current for pMOSFETs has been achieved. At the same time, high stress GC liner-SiN can improve nMOSFET performance for the <100> channel orientation.

For transistor performance comparison, follow this link.

 

Poly-gate Replacement Through Contact Hole (PRETCH): A new method for High-K/Metal gate and multi-oxide implementation on chip
S. Harrison, P. Coronel, A. Cros, R. Cerutti, F. Leverd, A. Beverina, R. Wacquez, J. Bustos, D. Delille, B. Tavel, D. Barge, J. Bienacel, M. P. Samson, F. Martin, S. Maitrejean, D. Munteanu, J. L. Autran, T. Skotnicki

This paper reports on a novel replacement gate technology, where the poly-Si gate material is etched through the contact holes by a SF6 based plasma with high selectivity to the gate oxide and the silicides. After poly-Si removaland BOE clean, new gate oxides with reduced thickness or high k dielectrics can be deposited followed by the metal gate material. In one example, the gate dielectric is HfO2 with an EOT of 1.8 nm (4 nm physical thickness) and the gate material is TiN.

For transistor performance comparison, follow this link.

 

Sub 30 nm Multi-Bridge-Channel MOSFET(MBCFET) with Metal Gate Electrode for Ultra High Performance Application
Eun-Jung Yoon, Sung-Young Lee, Sung-Min Kim, Min-Sang Kim, Sung Hwan Kim, Li Ming, Sungdae Suk, Kyounghawn Yeo, Chang Woo Oh, Jung-dong Choe, Donguk Choi, Dong-Won Kim, Donggun Park, Kinam Kim and Byung-Il Ryu

Multiple layers of Si and SiGe are used to form multi bridge channel devices. A selective SiGe etch is used to empty the channels andd to fill them with gate dielectrics and electrodes similar to the silicon on nothing (SON) integration scheme. Very large drive currents are reported.

For transistor performance comparison, follow this link.

 

45nm nMOSFET with Metal Gate on Thin SiON Driving 1150 microamps/micrometer and Off-state of 10nA/micrometer
K. Henson, R.J.P. Lander, M. Demand, C.J.J. Dachs, B. Kaczer, W. Deweerd, T. Schram, Z. Tokei, J.C. Hooker, F.N. Cubaynes, S. Beckx, W. Boullart, B. Coenegrachts, J. Vertommen, O. Richard, H. Bender, W. Vandervorst, M. Kaiser, J-L. Everaert, M. Jurczak, S. Biesemans

This paper reports on a nMOS devices with PVD TaN gate on 1.2 nm EOT SiON. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes.

For transistor performance comparison, follow this link.

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