Plasma Technology for Advanced Devices


Volume 19: November 2004

Plasma Etching

Production and loss mechanisms of SiClx etch products during silicon etching in a high density HBr/Cl2/O2 plasma
G. Cunge, M. Kogelschatz, N. Sadeghi
J. Appl. Phys. 96 (2004) 4578

This paper confirms previous mass spectroscopic studies (G. Cunge, et al.; J. Vac. Sci. Technol. B 20 (2002), 2137 / Clarycon Literature Digest vol. 4) with a broadband ultraviolet absorption spectroscopy study of the same plasma chemistry / substrate system. A comparison of the results obtained in both studies reveals that while the SiCl2 concentration is about 20 times larger than the SiCl concentration, it appears that the SiCl+ ion flux is approximately six times larger than the SiCl2+ flux. In addition, while SiClx etch products represent only a small fraction of the total species density in the reactor chamber (typically 1%–2%), the SiClx+ ion flux account for <40% of the total ion flux impinging on the chamber wall (about 1 μA cm-2 under these conditions). It is concluded that SiCl2 is the dominant radical in the plasma because it is an etch product from both the wafer and the reactor walls. The electron impact dissociative ionization of this radical produces large amounts of SiCl+ ions, which is the dominant ion in the system.

Advanced Devices

A Simplified Hybrid Orientation Technology (SHOT) for High Performance CMOS
B. Doris, Y. Zhang, D. Fried, J. Beintner, O. Documaci, W. Natzle, H. Zhu, D. Boyd, J. Holt, J. Petrus, J.T. Yates, T. Dyer, P. Saunders, M. Steen, E. Nowak, M. Ieong
2004 Symposium on VLSI Technology, Digest of Technical Papers, p. 86

Circuits with (110) oriented pMOS FinFETs and (100) oriented nMOS UTSOI devices have been demonstrated. The process flow uses the previously reported Simplified Hybrid Orientation Technology (SHOT) to generate FinFET and UTSOI devices with optimal surface orientation for critical path and PDSOI devices for non critical path devices. The patterning process includes the formation of a silicon oxide hardmask layer with Si cap layer, the opening of this hardmask stack and the selective trim of the oxide layer for the FinFET device (while the UTSOI and PDSOI devices are covered). This is hardmask trim is presumably done in a non-plasma process to achieve an isotropis oxide etch with very good selectivity to silicon. Subsequently, the Si cap layer is removed and the SOI layer is etched. In a last step, the active region of the UTSOI is thinned selectively while the FinFET and PDSOI devices are protected The reported drive current of the pFinFET is with 810 microamps/micrometer at Vdd=1.2V among the best ever reported.

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