Plasma Technology for Advanced Devices
Volume 13: December 2003
“Discrete Dislocation Dynamics Study of Strained-Layer Relaxation”
Strained silicon has become one of the main focal points in advanced device development. This paper presents numerical simulations to follow the initial density of dislocation loops in an infinite strained layer to the point where the dislocations stopped moving. The investigation indicate the presence of mechanisms to immobilize stress relaxation prematurely thus leaving the layer with more stress than previously assumed. The authors point out that the influence of grading layers and buried oxide layers should be studied experimentally.
Spatial Light Modulators
“Operation of special light modulators in DUV light”
This paper describes the fabrication flow of the SLM developed by the Fraunhofer Institute for Microelectronic Circuits and Systems (FhG-IMS) which is used in a pattern generator for DUV laser mask writing by Micronic Laser Systems. A fatal performance failure caused by DUV exposure of the SLM is discussed. A thin TiN layer on top of the mirror addressing electrodes is oxidized during the operation in DUV light causing so called “bleaching” of the device. The effect can be eliminated by purging of the SLM with gases such as argon, helium, nitrogen, and forming gas.
“High-resolution maskless lithography”
This paper presents a high-resolution maskless lithography system with the Texas Instruments super video graphic array (SVGA) digital micromirror device (DMD) as the spatial and temporal light modulator. Results indicate consistent 1.8-μm line space resolution across a field width of 8.47 mm.
“Polymer-on-Polymer Stamping on Micro- and Nano-Scales”
This report shows the feasibility to reach sub-micrometer resolution in polymer on polymer stamping. The investigated system is PDAC (poly(diallyldimethylammonium chloride) on a PDMS (polydimethylsiloxane) stamp. A rigid stamping apparatus an spin coating of the stamp with fine tuned ink solutions was required.
Plasma Etching: Dielectric Etch
“Redeposition of etch products on sidewalls during SiO2 etching in a fluorocarbon plasma. IV. Effects of substrate temperature in a CF4 plasma”
This is the fourth report in a series of papers on experiments in the Faraday cage setup with vertically placed substrates in a plasma etch chamber at the Seoul National University (see also http://www.clarycon.com/literature_v2.html). MERIE and ICP plasma conditions were studied. Lateral etching was more sensitive to the wafer temperature than vertical etching. The latter is more pronounced for the ICP plasma conditions used in this particular experiment. As the substrate temperature increases, the F/C ratio and Si/O ratios decrease.
“Review of Trench and via plasma etch issues for copper dual damascene in undoped and fluorine-doped silicate glass oxide”
Excellent review article about integration and plasma etch issues. Very comprehensive in both the integration and plasma etch aspects.
Plasma Etching: Metal Etch
“Dry etching characteristics of TiN film using Ar/CHF3, Ar/Cl2, and Ar/BCl3 gas chemistries in an inductively coupled plasma”
Profile and etch rate effects are studied and etch mechanisms are proposed based on XPS and AES studies. Chlorine is found to be most effective to produce high etch rates while BCl3 and CHF3 can be used to control the profile taper. TiF3 and BOxNy were found on the etched surface for the Ar/CHF3 and Ar/BCl3 etch chemistries, respectively.
Plasma Etching: Silicon Etch
“Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching”
This article describes an effect that is increasingly becoming critical in the manufacturing of advanced devices, the recessing of the gate oxide during the overetch step of the polysilicon gate etch process. Gate oxide recessing is an ion-enhanced process with an activation energy of 0.02 eV and was modeled using the Deal-Grove thermal oxidation model with the inclusion of a depth-dependent reaction constant. The plasma oxidation and silicon loss are reduced by using a shorter overetch time, lower source and bias power, lower substrate temperature, and lower O2 flow. Gate oxide recess as low ass 18 Å is reported.
“Impact of chemistry on profile control of resist masked silicon gates etched in high dessity halogen-based plasmas”
Critical dimension (CD) control during silicon gate etching has been studied by high resolution cross section SEM. It has been observed that CF4 addition to a typical HBr/Cl2/O2 chemistry leads to a decrease of the profile differences between dense and isolated lines. This is explained by a change in the passivation layer deposition mechanism. CFx like passivation layers originate from one precursor while SiOx layers require both SiClx and O precursors. It is found that CF4 addition results in enhanced ARDE for very dense lines which causes profile distortions during the softlanding and overetch steps.
Plasma Etching: Modeling
“Simultaneous, multilayer plasma etching and deposition of fluorocarbon layers on silicon”
This model of plasma etching and fluorocarbon deposition on a silicon substrate is based on Langmuir kinetics applied a stack of monolayers. The Langmuir kinetics apply to a depth where ions can still break the polymer bonds. The model assumes further the diffusion of the fluorine etchant through the polymer layer to the silicon surface where it reacts. The deposition and etching of the polymer layer under plasma exposure is ion assisted. An analytical expression of the deposition and etch processes for the fluorocarbon layer on silicon is derived.
“Modeling of fluorine-based high-density plasma etching of aniotropic silicon trenches with oxygen sidewall passivation”
Monte Carlo simulations of deep trench etching by SF6/O2 show that aspect ratio dependent etching is caused by the depletion of fluorine radicals due to Knudsen transport. This can be compensated by the depletion of oxygen surface coverage as the aspect ratio decreases and hence an increase of the number of available reaction sites.