Plasma Technology for Advanced Devices

4/17/05

EE Times reported this week that Intel "may drop the use of a high-k dielectric in the transistor gate stack at the 45-nanometer manufacturing process node". This appears to be a departure from plans to use highk and metal gate at 45 nm. The completion of the selction of these material was announced in November 2003. Intel presented a paper on a TiN/HfOx transistor with strained silicon shortly after this announcement during the IEDM conference 2003. During the same conference, AMD indicated that it would focus on fully depleted SOI and three dimensional devices as a solution for the 45 nm node.

Despite this latest announcement about the demished chances for high k in 45 nm Intel devices, the company said that it is working on a second generation high k material.An overview about Intels high k technology development can be found on Intel's website.

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