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|  | | Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation
by P. D. Agnello
IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002, page 317 | |  | |
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| White Papers on Advanced Process Control
at
www.straatum.com | | "Identifying Front-End Challenges for 90 nm Design" G. Higashi, Th. Lill
published in EE Times Asia (for Korean version click here) | | |
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| Polysilicon Planarization and Plug Recess Etching in a Decoupled Plasma Source Chamber Using Two Endpoint Techniques
George A. Kaplita, Stefan Schmitz, Rajiv Ranade, Swami Mathad
at www-3.ibm.com | |  | | |
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"Photoresist Mask Faceting, Sidewall Deposition, and Microtrenching"
Arpan Mahorowala and Herbert H. Sawin
at: www/plasma-processing.com | |
"Simulation of Profile Evolution Using Cellular Representation of Feature Composition and Monte Carlo Computation of Flux and Surface Kinetics"
Arpan Mahorowala and Herbert H. Sawin
at: www/plasma-processing.com
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| Powered by 
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"Experimental Characterization of Polysilicon Profiles"
Arpan Mahorowala and Herbert H. Sawin
at: www/plasma-processing.com | | |
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"Developing a WSix Gate Etch Process with CD Bias Uniformity less than 3nm"
Wilfred Pau, Meihua Shen, Shashank Deshmukh, Takanori Nishizawa
at: www.future-fab.com
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| "Technology Innovations and Process Integration for Sub-100nm Gate Patterning"
Meihua Shen, Wilfred Pau, Nicolas Gani, Jianping Wen, Shashank Deshmukh, Thorsten Lill, Theodoros Panagopoulos and John Holland, Jian Zhang, Hanming Wu and Guqing Xing | |  | | |
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"An Introduction of Etch Process" Ho Young Kang | |  | | |
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"Chemical reaction Mechanisms for Modeling the Fluorocarbon Plasma Etch of Silicon Oxide and Related Materials "
Pauline Ho, Justine E. Johannes, Richard J. Buss, and Ellen Meeks
Sandia National Laboratories | |  | | |
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