Plasma Technology for Advanced Devices

Clarycon News Archive: Intel

1/27/2007
Intel announces the used of metal gates and hafnium based high k dielectrics in the 45nm Penryn processor. This 45nm process technology improves transistor density by approximately two times that of the previous generation, allowing Intel to either increase the overall transistor count or to make processors smaller. Because the 45nm transistors are smaller than the previous generation, they take less energy to switch on and off, reducing active switching power by approximately 30 percent. Intel will use copper wires with a low-k dielectric for its 45nm interconnects for increased performance and lower power consumption. It will also use innovative design rules and advanced mask techniques to extend the use of 193nm dry lithography. “The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s,” said Intel Co-Founder Gordon Moore. Source: Businesswire
A TEM allegedly form the Intel 45 nm gate stack can be found here.

4/17/2005
EE Times reported this week that Intel "may drop the use of a high-k dielectric in the transistor gate stack at the 45-nanometer manufacturing process node". This appears to be a departure from plans to use highk and metal gate at 45 nm. The completion of the selction of these material was announced in November 2003. Intel presented a paper on a TiN/HfOx transistor with strained silicon shortly after this announcement during the IEDM conference 2003. During the same conference, AMD indicated that it would focus on fully depleted SOI and three dimensional devices as a solution for the 45 nm node. An overview about Intels high k technology development can be found on Intel's webite. Despite this latest announcement about the demished chances for high k in 45 nm Intel devices, the company said that it is working on a second generation high k material.

2/19/2004
Intel Corp.annouunces the worlds first 90 nm NOR flash memory. Source: www.intel.com

1/14/2004
Nanosys Inc. announces that they have entered into a collaborative agreement with Intel to investigate using nanotechnology for future memory systems. Under the agreement, Intel will help support nano-related technology efforts at Nanosys for possible use in memory products. According to the agreement, Nanosys and Intel will work together exclusively on certain areas of memory related technologies for a set period of time.
Source:
www.nanosysinc.com

12/7/2003
Intel reports at the IEDM conference on a strained PMOS transistor structure that features an epitaxially grown
strained SiGe film embedded in the source drain regions creating an uniaxial compressive strain in the channel.

10/15/2003
Intel Corp., which had cut 157-nm lithography from its plans, joins an IMEC industrial affiliation collaborative research program around immersion for both 193-nm and 157-nm wavelength lithography. Source: Silicon Strategies

6/12/2003
Intel Corp. reveales at the VLSI symposium in Kyoto new details of its advanced “tri-gate” transistor design, claiming the technology could be deployed at the 45-nm node in 2007. Source: '

5/22/2003
Intel announces that it will use 193 nm lithography all the way down to the 45 nm node. Source: San Jose Mercury News

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