Plasma Technology for Advanced Devices

Critical Dimension (CD) Control During Gate Etching

The term CD control describes requirements and methods to transfer a critical dimension of a mask (for instance the length of a transistor gate) into the final dimension of the etched feature (slide 1). During etching, a sidewall passivation layer is formed. This layer with it’s finite thickness constitutes a deviation from the original mask dimension. Critical dimension control is therefore sidewall passivation thickness control across die (dense and isolated lines etc.), across wafer, and wafer-to-wafer. The thickness of the passivation layer in turn is controlled by the balance between etch and deposition within each etching step and for all steps in combination. To achieve the highest possible pattern fidelity in advanced gate etch process, several hundred process parameters have to be selected and controlled in such a way that all features across a 300 mm wafer and among thousands of wafers do not deviate by more than 3 to 6 nm or 10 to 20 atoms.

Slide 2 shows the reaction mechanism and EELS analysis results for a poly-Si gate etch with HBr/Cl2/O2 chemistry. The EELS shows that the passivation layer on the mask and gate sidewalls is thicker than the CD deviation allowed across the entire wafer for sub 100 nm technology nodes. The passivation thickness is bettween 0 nm on the bottom and 9 nm on the top of the sidewall.

Slide 3 introduces the definition of CD bias and shows that it is determined by the sidewall passivation layer thickness. This passivsation layer is typically thicker in the isolated than in the dense area.

The definition of CD bias microloading is introduced in slide 4.

Anisotropic etching is a combination of isotropic etching and passivation deposition. Different etch processes will therefore show differences in the CD microloading depending on the relationship between deposition and etch (slide 5).

The etch proximity effect can be illustrated in a graph that shows CD bias microloading as a function of the CD bias. Different etch processes show dramatically different etch proximity effects depending on the underlaying etch mechanisms (slide 6).

Slide 7 shows the analysis of the etch proximity effect for a traditional HBr/Cl2/O2 poly-Si etch process in comparison to a CF4 added process (all other gases remain the same). When process parameter in main etch step are randomly varied, the CF4 added process shows clearly a better CD microloading behavior.

Sllde 8 gives a tentative explanation for the difference in the etch proximity effect for the traditional poly-Si and the CF4 added process. The underlaying root cause is that the passivation layer formation results from the competition between deposition and etch processes. If etch and deposition species originate both in the gas phase and show a similar aspect ratio dependence, the resulting passivation layer thickness should be less sensitive to the aspect ratio, i.e. open area.

Another example for etch proximity effects is given in slide 9 for a HBr/O2 based resist trim process. When CF4 is added to the chemistry, the dense lines show a larger CD bias (increased CD loss) compared to the Ar added process. This can be used in gate etching to compensate lithographic (optical) proximity effects during the resist trim step.

Slide 10 gives a tentative explanation for the proximity effect during resist trim.

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